During integrated circuit (IC) manufacturing on semiconductor wafer, wafer-level testing plays a crucial role to guarantee the quality of the ICs, particularly as the hot spots such as voids and defects (e.g., polysilicon voids (PO voids), dummy polysilicon voids (DPO voids) and work function metal (WFM)) become more critical for yield with technology evolution (e.g., miniaturization, dimension shrink). In the known approaches, after the semiconductor wafer is completed through the semiconductor processing and prior to the dicing process of the ICs from the semiconductor wafer, Wafer Acceptance Test (WAT) is performed to determine whether the semiconductor wafer meet criteria for an acceptable wafer.
For example, when manufacturing ICs including metal oxide semiconductor (MOS) transistors on a semiconductor wafer, the test line in scribe lines of the semiconductor wafer are tested, wherein each test line may have few MOS transistors (e.g., 4 MOS transistors), and the drain terminal and the gate terminal of the MOS transistors in a test line are electrically connected to each other. In the known approaches, the threshold voltage (Vth) and drain current when the MOS transistors in a saturation mode (Idsat) are monitored to determine the defects (e.g., voids) of the ICs.
However, since there are few MOS transistors (e.g., 4 transistors) per a test line and the gate terminal and the drain terminal of the MOS transistors in each of the test line are electrically connected to each other, the testing speed is slow and the accuracy is limited.